Integrated circuits may be susceptible to functional failures under certain conditions. One type of integrated circuit may include integrated circuit having programmable logic, e.g., programmable logic devices (PLDs). PLDs are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, and so forth.
Well-studied occurrences in circuitry are event upsets which include Single Event Upset (SEU) and Multiple Bits Upset (MBU). SEU and MBU are inadvertent changes in state of a circuit caused by an external energy source such as, cosmic rays, alpha particles, energetic neutrons, and the like. The energetic particles may randomly strike a semiconductor device and penetrate into the substrate (e.g., transistor source and drain regions) of the semiconductor device. These particle strikes create pairs of electrons and holes, which in turn cause undesirable transients that may upset circuit elements, for example, flipping the logic state of a latch or other memory element. As fabrication geometries and supply voltages continue to decrease, SEU and MBU problems become more severe. As a result, efforts to detect and correct effects caused by SEU and MBU are increasingly important.
In an integrated circuit including programmable logic, such as an FPGA, configuration memory defines how the FPGA's resources, e.g., CLBs, IOBs, and interconnect structure, are configured. Inadvertent state changes in the configuration memory resulting from SEU transients may alter the FPGA's operation.
Each programmable tile of an FPGA typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
For all types of integrated circuits including programmable logic, e.g., PLDs, the functionality of the programmable portion of the device is controlled by data bits or bitstream provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory.
An approach to remedy SEU related issues in configuration memory cells is to use triple modular redundancy (TMR). Utilizing the TMR approach, individual memory cells are replaced with three sets of memory cells, where the outcome of at least two of the three sets controls FPGA operation. However, implementing TMR in an FPGA has an undesirable cost function including an increase in the size and cost of a design in the FPGA. Also, TMR may mitigate a SEU affects, however, MBU and accumulation of SEUs may render the TMR approach ineffective. In general, PLDs are also vulnerable to single event function interrupt. The single function interrupts may affect the operation of the PLD to the point of failure. A method to curb the effects of single event function interrupt includes deploying redundant devices.
Accordingly, it would be desirable to provide a method and apparatus to correct effects caused by SEU and MBU occurrences in an integrated circuit.